- DSP architecture
- DSP architecture Signalprozessorarchitektur f, Havard-Mikroprozessorarchitektur f (getrennter Programm- und Datenbus, MULU)
English-German dictionary of Electrical Engineering and Electronics. 2013.
English-German dictionary of Electrical Engineering and Electronics. 2013.
Architecture ARM — Les architectures ARM, développées par ARM Ltd, sont des architectures RISC 32 bits. Dotés d une architecture relativement plus simple que d autres familles de processeurs, et bénéficiant d une faible consommation, les processeurs ARM sont… … Wikipédia en Français
Architecture Harvard — Schéma de l architecture Harvard L’architecture de type Harvard est une conception de microprocesseurs qui sépare physiquement la mémoire de données et la mémoire programme. L’accès à chacune des deux mémoires s’effectue via deux bus distincts.… … Wikipédia en Français
CEVA-X DSP — The CEVA X family of DSP cores from CEVA is based on the company s latest pioneering DSP architecture. The CEVA X architecture has a unique mix of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) architectures. The… … Wikipedia
ARM architecture — This article is about a computer processor architecture. For other uses, see ARM (disambiguation). Logo ARM Designer ARM Holdings Bits … Wikipedia
Jazz DSP — The Jazz DSP, by [http://www.improvsys.com Improv Systems] , is a VLIW embedded digital siginal processor architecture with a 2 stage instruction pipeline, and single cycle execution units. The baseline DSP includes one arithmetic logic unit… … Wikipedia
TRIPS architecture — TRIPS is a new microprocessor architecture being designed by a team at the University of Texas at Austin in conjunction with IBM. TRIPS uses a new instruction set architecture that is designed to be easily broken down into large groups of… … Wikipedia
MIPS architecture — MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a RISC microprocessor architecture developed by MIPS Technologies. As of|1999|alt=By the late 1990s it was estimated that one in three RISC chips produced were … Wikipedia
Modified Harvard architecture — The Modified Harvard Architecture is a variation of the Harvard computer architecture that allows the contents of the instruction memory to be accessed as if it were data. Most modern computers that are documented as Harvard Architecture are, in… … Wikipedia
Super Harvard Architecture Single-Chip Computer — The Super Harvard Architecture Single Chip Computer (SHARC) is a high performance floating point and fixed point DSP from Analog Devices,not to be confused with Hitachi s SuperH (SH) microprocessor. SHARC is used in a variety of signal processing … Wikipedia
Transport triggered architecture — (TTA) вариант архитектуры микропроцессоров, в которой программы непосредственно управляют внутренними соединениями (шинами) между блоками процессора (например, АЛУ, Регистровый файл). Вычисления являются побочным эффектом передачи данных… … Википедия
Software Communications Architecture Reference Implementation — The Software Communications Architecture Reference Implementation (SCARI) is an implementation of the US Military s Joint Program Executive Office (JPEO) Software Communications Architecture (SCA) Core Framework. It was developed mainly by the… … Wikipedia